High Voltage ESD Protection Apparatus

ABSTRACT

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.16/227,726, filed on Dec. 20, 2018, which is a continuation of U.S.patent application Ser. No. 15/165,832, filed on May 26, 2016, now U.S.Pat. No. 10,163,891 issued on Dec. 25, 2018, which is a divisional ofU.S. patent application Ser. No. 13/243,688, filed on Sep. 23, 2011, nowU.S. Pat. No. 9,356,012 issued on May 31, 2016, which applications areincorporated herein by reference.

BACKGROUND

Electrostatic discharge (ESD) is a rapid discharge that flows betweentwo objects due to the build-up of static charge. ESD may destroysemiconductor devices because the rapid discharge can produce arelatively large current. In order to reduce the semiconductor failuresdue to ESD, ESD protection circuits have been developed to provide acurrent discharge path. When an ESD event occurs, the discharge currentis conducted through the discharge path without going through theinternal circuits to be protected.

In the semiconductor technology, ESD protection solutions such as NMOStransistors, Silicon-Controlled Rectifiers (SCRs) and RC triggered PMOStransistors are widely used. Each ESD protection device may comprise adetection circuit and an ESD current discharge path. For example, an RCtriggered ESD protection circuit may comprise a discharge transistor, adriver and an ESD spike detection circuit. The ESD spike detectioncircuit may include a resistance element and a capacitance elementconnected in series to form an RC detection circuit. The node betweenthe resistance element and the capacitance element is coupled to thegate of the discharge transistor via the driver. The time constantformed by the resistance element and the capacitance element is sochosen that the discharge transistor is turned off when the ESDprotection device operates in a normal power up mode. On the other hand,the discharge transistor is turned on when an ESD spike occurs at apower bus to which the ESD protection circuit is coupled. The turn-on ofthe discharge transistor may provide a bypass of the ESD current fromthe power bus to ground so as to clamp the voltage of the power bus to alevel below the maximum rating voltage to which the internal circuit isspecified, so that it helps to prevent the large voltage spike fromdamaging the internal circuits being protected.

Similarly, a PNP transistor can be used as an ESD protection device.More particularly, the emitter of the PNP transistor is coupled to aninput/output (I/O) pad of an integrated circuit and the collector of thePNP transistor is coupled to ground. When an ESD event occurs, anexternal voltage across the I/O pad and ground increases beyond thereverse-bias breakdown voltage of the PNP transistor. As a result, aconductive path is established between the emitter and the collector ofthe PNP transistor. Such a conductive path allows the large amount ofESD energy to be discharged in a relatively short amount of time. As aconsequence, the internal circuit components of the integrated circuitcan be protected from being damaged by the ESD event.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with an embodiment;

FIG. 2 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 1;

FIG. 3 illustrates breakdown voltage curves of a conventional ESDprotection circuit such as a PNP transistor and the ESD protectioncircuit in FIG. 2;

FIG. 4 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with another embodiment;

FIG. 5 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 4;

FIG. 6 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with yet another embodiment;

FIG. 7 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 6;

FIG. 8 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with yet another embodiment;

FIG. 9 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 8;

FIG. 10 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with yet another embodiment;

FIG. 11 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 10;

FIG. 12 illustrates an integrated circuit level ESD protection diagramin accordance with an embodiment; and

FIG. 13 illustrates a further ESD protection scheme by employing aplurality of ESD protection circuits in series connection between an I/Opad and a VSS pad.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the variousembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, an NPN transistor based electrostaticdischarge (ESD) protection device. The invention may also be applied,however, to a variety of ESD protection devices.

FIG. 1 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with an embodiment. The ESDprotection structure 100 includes a first P+ region 102, a second P+region 108, a first N+ region 106, a first isolation region 142, asecond isolation region 144, a third isolation region 146 and a fourthisolation region 148. The ESD protection structure 100 further comprisesa shallow p-type well 112 and shallow n-type well 114 and 116. Forsimplicity, throughout the description, the shallow p-type well 112 andthe shallow n-type well 114 and 116 are alternatively referred to as aSHP region 112, a first SHN region 114 and a second SHN region 116respectively. In one embodiment, the SHP region 112, the first SHNregion 114 and the second SHN region 116 have a depth of about 1 μm.

The ESD protection structure 100 further comprises a first high voltageP well (HVPW) region 122, a high voltage N well (HVNW) region 124 and asecond HVPW region 126. As shown in FIG. 1, both the first HVPW region122 and the HVNW region 124 are formed on an N+ buried layer (NBL) 132.The NBL 132 is commonly used in the art, and hence is not discussed infurther detail. Both the SHP region 112 and the first SHN region 114 areformed in the HVPW 122. More particularly, as shown in FIG. 1, an upperportion of the SHP region 112 and an upper portion of the first SHNregion 114 are separated by the second isolation region 144. A bottomportion of the SHP region 112 and a bottom portion of the first SHNregion 114 are enclosed by the HVPW region 122. Likewise, the second SHPregion 116 has an upper portion formed between the third isolationregion 146 and the fourth isolation region 148 and a bottom portionenclosed by the HVNW region 124.

The first P+ region 102 is formed on the SHP region 112. The first P+region 102 is separated from the first SHN region 114 by the secondisolation region 144. The N+ region 106 is formed on the second SHNregion 116. The second P+ region 108 is formed on the second HVPW 126.As shown in FIG. 1, the N+ region 106 is separated from the first SHNregion 114 by the third isolation region 146. In addition, the N+ region106 is separated from the second P+ region 108 by the fourth isolationregion 148.

In FIG. 1, there may be a p-type metal contact 152 formed on the firstSHN region 114. As a result, the p-type metal contact 152 and the firstSHN region 114 form a diode junction. Such a diode junction helps toincrease the breakdown voltage of the ESD protection device 100. Thedetailed explanation of the p-type metal contact 152 will be describedbelow with respect to FIG. 2 and FIG. 3. In accordance with anembodiment, the p-type metal contact 152 comprises cobalt silicide(CoSi2). It should be noted that while FIG. 1 illustrates a p-type metalcontact 152 formed on the first SHN 114, one skilled in the art willrecognize that other metal contacts are necessary for the first P+region 102 and the N+ region 106. Indeed, the metal contacts on thefirst P+ region 102 and the N+ region 106 are semiconductor contactsthat form low resistance connections between the ESD protection device100 and external terminals (not shown).

The SHP region 112, the first SHN region 114 and the second SHN region116 are fabricated in a low voltage CMOS process. In accordance with anembodiment, the SHP region 112, the first SHN region 114 and the secondSHN region 116 are fabricated in a 5V CMOS process. It should further benoted that while the SHP region 112, the first SHN region 114 and thesecond SHN region 116 appear to be similar in FIG. 1, one person skilledin the art will recognize that it is merely an example. The SHP region112, the first SHN region 114 and the second SHN region 116 may haveunequal dimensions or doping concentrations.

In accordance with an embodiment, the first P+ region 102, the second P+region 108 and the N+ region 106 are highly doped. The first P+ region102, the second P+ region 108 and the N+ region 106 have a dopingdensity of between about 10²⁰/cm³ and 10²¹/cm³. In addition, the SHPregion 112, the first SHN region 114 and the second SHN region 116 areheavily doped regions. The SHP region 112 has a doping density ofbetween about 10¹⁷/cm³ and 10¹⁸/cm³. The first SHN region 114 and thesecond SHN region 116 have a doping density of between about 10¹⁷/cm³and 10¹⁸/cm³. Furthermore, in accordance with an embodiment, the firstHVPW region 122 has a doping density of about 10¹⁷/cm³. Likewise, theHVPW region 124 and the second HVPW region 126 have a doping density of10¹⁷/cm³.

It should be noted that the doping technique used in the previousexample is selected purely for demonstration purposes and is notintended to limit the various embodiments to any particular dopingtechnique. One skilled in the art will recognize that alternateembodiment could be employed (such as employing the diffusiontechnique).

The isolation regions 142, 144, 146 and 148 are used to isolate activeregions so as to prevent leakage current from flowing between adjacentactive regions. The isolation region (e.g., the first isolation region142) can be formed by various ways (e.g., thermally grown, deposited)and materials (e.g., silicon oxide, silicon nitride). In accordance withan embodiment, the isolation regions (e.g., the first isolation region142) may be fabricated by a surface trench isolation (STI) technique.

In accordance with an embodiment, the ESD protection structure 100 maycomprise two depletion regions. A first depletion region is formedbetween the HVNW region 124 and the first HVPW region 122. One skilledin the art will recognize that the first depletion region can provide abreakdown voltage when the first depletion region is reverse biasedduring an ESD event. The detailed operation of the breakdown voltage ofthe ESD protection structure 100 will be described below with respect toFIG. 2 and FIG. 3. In addition, a second depletion region is formedbetween the p-type metal contact 152 and the first SHN region 114. Sincethe second depletion region is connected in series with the firstdepletion region, the second depletion region may provide additionalbreakdown voltage protection.

In FIG. 1, the ESD protection structure 100 may provide an on-chip ESDprotection solution. For ESD protection applications, the N+ region 106is typically coupled to an input/output (I/O) pad and the p-type metalcontact 152 is typically coupled to a VSS pad, which is typicallygrounded or coupled to a power supply. An advantageous feature of thedescribed embodiment is that the second depletion region formed by thep-type metal contact 152 and the first SHN region 114 provides extra ESDprotection headroom as well as reliable protection.

FIG. 2 illustrates an equivalent circuit diagram of the ESD protectionstructure illustrated in FIG. 1. The equivalent circuit of the ESDprotection structure 100 illustrated in FIG. 1 includes a diode 210 andan NPN transistor 220. Referring again to FIG. 1, the p-type metalcontact 152 is formed on the first SHN region 114. The junction betweenthe p-type metal contact 152 and the first SHN region 114 forms thediode 210 as shown in FIG. 2. The diode 210 has a cathode and an anode.The cathode is located in the first SHN region 114. The anode is locatedin the p-type metal contact 152. In accordance with an embodiment, thediode 210 has a typical breakdown voltage of 10V. However, as one ofordinary skill in the art will recognize that the diode 210 and itsassociated semiconductor structure is merely exemplary and is notintended to limit various embodiments in any fashion. By selectingdifferent diffusion parameters, any suitable breakdown voltage ratingmay be utilized in the ESD protection circuit described above.

The NPN transistor 220 has an emitter 212, a base 216 and a collector214. The emitter 212, the base 216 and the collector 214 are formed bythe first SHN region 114, the first P+ region 102 and the N+ region 106respectively. The emitter 212 is electrically coupled to the cathode ofthe diode 210. The base 216 is either coupled to the emitter 212 orfloating. In sum, a simplified circuit diagram 200 depicts that thecorresponding circuit of the ESD protection structure 100 is formed by aseries connection of the diode 210 and the NPN transistor 220.

However, it should be recognized that while FIG. 2 illustrates the ESDprotection circuit with one diode and one NPN transistor (e.g., diode210 and NPN transistor 220), the ESD protection circuit couldaccommodate any numbers of diodes and NPN transistors. Furthermore, itis understood that the ESD protection circuit may be implemented using aplurality of diodes or NPN transistors in series connection. On theother hand, other configurations of a plurality of diodes and NPNtransistors such as parallel-connected diodes coupled toparallel-connected NPN transistors are also within the contemplatedscope of this embodiment.

As known in the art, the NPN transistor 220 has a breakdown voltage.When a large voltage spike is applied between the collector 214 and theemitter 212, the NPN transistor 220 may experience an avalanchebreakdown in which a large current is allowed to flow from the collector214 to the emitter 212. The current path from the collector 214 to theemitter 212 may provide a bypass of the ESD current and clamp thevoltage between the collector 214 and the emitter 212 to a level belowthe maximum rating voltage of the internal circuit, so that it helps toprevent the large voltage spike from damaging the internal circuitsbeing protected. Similarly, the diode 210 has a breakdown voltage (e.g.,10V) when a voltage is applied between the cathode and the anode of thediode 210. In sum, the ESD protection circuit 200 has a breakdownvoltage equivalent to the NPN transistor's 220 breakdown voltage plusthe diode's 210 breakdown voltage.

The ESD protection circuit 200 is typically placed at an I/O pad and aVSS of a device to be protected (not shown but illustrated in FIG. 12).The first N+ region 106 is typically coupled to the I/O pad and thep-type metal contact 152 is typically coupled to the VSS, which istypically grounded. If an ESD event occurs, a voltage spike is appliedbetween the first N+ region 106 and the p-type metal contact 152.Firstly, both the diode 210 and the NPN transistor 220 experience thevoltage spike, which may exceed the breakdown voltages of the diode 210and the NPN transistor 220. In response to the voltage spike, the NPNtransistor 220 may enter an avalanche conduction mode. Consequently, theNPN transistor 220 may provide a current path so that the ESD dischargecurrent can flow from the collector 214 to the emitter 212.

Furthermore, the diode 210 allows the ESD current to flow from thecathode to the anode when the voltage across the cathode and the anodeexceeds the breakdown voltage of the diode 210 (e.g., 10 y). Inaddition, the diode 210 may clamp the voltage between the cathode andthe anode to its breakdown voltage (e.g., 10 y). The conduction of boththe diode 210 and the NPN transistor 220 clamps the voltage between thecollector 214 and the anode of the diode 210 to a lower level so thatthe internal circuits coupled to the collector 214 can be protected.

It should be noted that both the diode 210 and the NPN transistor 220may turn on nearly simultaneously. However, for convenience thedescription above uses a slightly earlier turn-on of the NPN transistor220 as an example to describe the breakdown mechanism. It is understoodthat the turn-on sequence between the diode 210 and the NPN transistor220 plays no role in this embodiment. The breakdowns of twoseries-connected elements (e.g., diode 210 and NPN transistor 220) inthe ESD protection circuit 200 may be performed in any arbitrarysequence. However, the specifically discussed example above ispreferred.

FIG. 3 illustrates the breakdown voltage curves of a conventional ESDprotection circuit such as a PNP transistor and the ESD protectioncircuit 200 in FIG. 2. The horizontal axis of FIG. 3 represents the ESDvoltage across an ESD protection circuit (e.g., the ESD protectioncircuit 200). The vertical axis of FIG. 3 represents the ESD currentflowing through the ESD protection circuit. A curve 302 illustrates thecurrent flowing through a conventional ESD protection circuit as avoltage spike is applied. As shown in FIG. 3, the trigger voltage aswell as the breakdown voltage for a conventional ESD protection circuitis around 30V. On the curve 302, before the applied voltage reaches thetrigger voltage, the ESD current is approximately equal to zero. Oncethe applied ESD voltage exceeds the trigger voltage, the ESD currentincreases in proportion to the applied ESD voltage. In this embodiment,the peak ESD current of the conventional ESD protection circuit is up toabout 3 A with a breakdown voltage approximately 30V.

The curve 304 represents the I-V relationship for the ESD protectioncircuit 200 during an ESD event. As shown in FIG. 3, the trigger voltageas well as the breakdown voltage of the ESD protection circuit 200 isabout 40V. After a resulting breakdown, the curve 304 is about inparallel with the curve 302 but having a voltage gap, which is about 10Vas illustrated in FIG. 3. An advantageous feature of the describedembodiment is that the diode 210 helps to provide a higher ESD breakdownvoltage.

FIG. 4 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with another embodiment. FIG. 4 issimilar to FIG. 1, and hence is not discussed in detail to avoidunnecessary repetition. In comparison with FIG. 1, a third P+ region 404is formed on the first SHN region 114. As a result, a second depletionregion is formed by the third P+ region 404 and the first SHN region114. Similar to the second depletion region formed by a p-type metalcontact 152 and the first SHN region 114 in FIG. 1, the second depletionregion in FIG. 4 can provide addition breakdown voltage protection. FIG.5 illustrates an equivalent circuit diagram of the ESD protectionstructure 400 illustrated in FIG. 4. As shown in FIG. 5, the equivalentcircuit diagram of the ESD protection structure 400 is similar to thatshown in FIG. 2, and hence is not discussed in further detail to avoidunnecessary repetition.

FIG. 6 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with yet another embodiment. Thestructure configuration of FIG. 6 is similar to FIG. 1 except that FIG.6 comprises a PNP transistor rather than an NPN transistor. Incomparison with FIG. 1, each p-type region is replaced by itscorresponding n-type region. Likewise, each n-type region is replaced byits corresponding p-type region. The operation principles of the PNPtransistor based ESD protection structure 600 is similar to its NPNtransistor based counterpart shown in FIG. 1, and hence are notdiscussed in detail to avoid repetition.

It should be noted that in FIG. 6 the metal contact 652 is an n-typemetal contact. In accordance with an embodiment, the n-type metalcontact 652 may be formed of Titanium Nitride (TiN). As shown in FIG. 6,the n-type metal contact 652 is formed on the first SHP region 614. As aresult, a second depletion region is formed by the n-type metal contact652 and the first SHP region 614. Similar to the second depletion regionformed by a p-type metal contact 152 and the first SHN region 114 inFIG. 1, the second depletion region in FIG. 6 can provide extra headroomduring an ESD event.

FIG. 7 illustrates an equivalent circuit diagram of the ESD protectionstructure 600 illustrated in FIG. 6. As shown in FIG. 7, the equivalentcircuit diagram of the ESD protection structure 600 comprises a diode710 connected in series with a PNP transistor 720. During an ESD event,the operation principle of the equivalent circuit diagram 700 is similarto that of the equivalent circuit diagram 200 shown in FIG. 2, and henceis not discussed in detail herein.

FIG. 8 illustrates a simplified cross-sectional view of an ESDprotection structure 800 in accordance with yet another embodiment. TheESD protection structure 100 includes a P+ region 806, an N+ region 802,a SHP region 816, a SHN region 812 and an HVPW region 822. Both the SHPregion 816 and the SHN region 812 are formed in the HVPW 822. Moreparticularly, as shown in FIG. 8, an upper portion of the SHP region 816is formed between the third isolation region 146 and the fourthisolation region 148. An upper portion of the SHN region 812 is formedbetween the first isolation region 142 and the second isolation region144. A bottom portion of the SHP region 816 and a bottom portion of theSHN region 812 are enclosed by the HVPW 822. The P+ region 806 is formedon the SHP region 816. The N+ region 802 is formed on the HVPW region822. The N+ region 802 is separated from the SHN region 812 by thesecond isolation region 144. The N+ region 802 is separated from the P+region 806 by the third isolation region 146.

In FIG. 8, there may be a p-type metal contact 852 formed on the SHNregion 812. As a result, the p-type metal contact 852 and the SHN region812 form a diode junction. Such a diode junction helps to increase thebreakdown voltage of the ESD protection device 800. In accordance withan embodiment, the p-type metal contact 852 comprises CoSi2. The SHPregion 816 and the SHN region 812 are similar to the SHP region and theSHN region in FIG. 1, and hence are not discussed in further detailherein.

In accordance with an embodiment, the ESD protection structure 800 maycomprises two depletion regions. A first depletion region is formedbetween the N+ region 802 and the HVPW region 822. One skilled in theart will recognize that the first depletion region can provide abreakdown voltage when the first depletion region is reverse biasedduring an ESD event. In addition, a second depletion region is formedbetween the p-type metal contact 852 and the SHN region 812. Since thesecond depletion region is connected in series with the first depletionregion, the second depletion region may provide additional breakdownvoltage during an ESD event.

FIG. 9 illustrates an equivalent circuit diagram of the ESD protectionstructure 800 illustrated in FIG. 8. As shown in FIG. 9, the equivalentcircuit diagram of the ESD protection structure 900 comprises a diode910 connected in series with an NPN transistor 920. During an ESD event,the operation principle of the equivalent circuit diagram 900 is similarto that of the equivalent circuit diagram 200 shown in FIG. 2, and henceis not discussed in detail herein.

FIG. 10 illustrates a simplified cross-sectional view of an ESDprotection structure in accordance with yet another embodiment. Thestructure configuration of FIG. 10 is similar to FIG. 8 except that FIG.10 comprises a PNP transistor rather than an NPN resistor. In comparisonwith FIG. 8, each p-type region is replaced by its corresponding n-typeregion. Likewise, each n-type region is replaced by its correspondingp-type region. The operation principles of the PNP transistor based ESDprotection structure 1000 is similar to its NPN transistor basedcounterpart 800 shown in FIG. 8, and hence are not discussed in furtherdetail herein.

It should be noted that in FIG. 10 the metal contact 1052 is an n-typemetal contact. In accordance with an embodiment, the metal contact 1052may be formed of TiN. As shown in FIG. 10, the n-type metal contact 1052is formed on the SHP region 1012. As a result, a second depletion regionis formed by the n-type metal contact 1052 and the SHP region 1012.Similar to the second depletion region formed by a p-type metal contact852 and the SHN region 812 in FIG. 8, the second depletion region inFIG. 10 can provide extra headroom during an ESD event.

FIG. 11 illustrates an equivalent circuit diagram of the ESD protectionstructure 1000 illustrated in FIG. 10. As shown in FIG. 11, theequivalent circuit diagram of the ESD protection structure 1100comprises a diode 1110 connected in series with a PNP transistor 1120.During an ESD event, the operation principle of the equivalent circuitdiagram 1100 is similar to that of the equivalent circuit diagram 200shown in FIG. 2, and hence is not discussed in detail herein.

FIG. 12 illustrates an integrated circuit level ESD protection diagramin accordance with embodiment. An integrated circuit chip 1200 has a VDDpad 1208, an I/O pad 1206 and a VSS pad 1204. Internal circuits 1202 arecoupled to the VDD pad 1208 and VSS pad 1204. The internal circuits 1202further include an input coupled to the I/O pad 1206. The ESD protectioncircuit 200 is coupled between the I/O pad 1206 and the VSS pad 1204. Itshould be noted that the ESD protection circuit 200 is provided forillustrative purpose only. The ESD protection circuit between the I/Opad 1206 and the VSS pad 1204 may comprise any variations of the ESDprotection circuits 200 shown in FIG. 2. For example, the ESD protectioncircuit may be any of the ESD protection circuits 500, 700, 900 and 1100shown in FIG. 5, FIG. 7, FIG. 9 and FIG. 11 respectively.

When an ESD event occurs between the I/O pad 1206 and the VSS pad 1204,the ESD protection circuit 200 conducts the ESD current, and the turn-onof an ESD protection circuit (e.g., the ESD protection circuit 200)clamps the voltage between the I/O pad 1206 and the VSS pad 1204 belowthe maximum voltage to which the internal circuits 1202 are specified,so that the internal circuits 1202 coupled between the I/O pad 1206 andthe VSS pad 1204 are protected. An advantageous feature of the describedcircuit level ESD protection is the ESD protection circuit provides abypass for ESD current to flow so that the various circuit components ofthe internal circuit 1202 are protected.

It should be noted that the ESD protection circuit 200 may be coupledbetween the VDD pad 1208 and the VSS pad 1204 as indicated by the dashedline in FIG. 12. When an ESD event occurs between the VDD pad 1208 andthe VSS pad 1204, the conduction of the ESD protection circuit clampsthe voltage between the VDD pad 1208 and the VSS pad 1204, so that theinternal circuits such as internal circuits 1202 are protected. Inshort, the connection of the ESD device 200 in FIG. 12 is merely anexample, which should not unduly limit the scope of the claims. Oneskilled in the art will recognize many variations, alternatives, andmodifications. For example, the ESD protection circuit 200 may comprisea plurality of NPN transistors connected in series.

FIG. 13 illustrates a further ESD protection scheme by employing aplurality of ESD protection circuits in series connection between an I/Opad and a VSS pad. Similar to FIG. 12, FIG. 13 includes an integratedcircuit 1200, a VDD pad 1208, an I/O pad 1206, a VSS pad 1204 andinternal circuits 1202. However, FIG. 13 further includes a seriesconnection of ESD protection circuits electrically coupled to the I/Opad 1206 and the VSS pad 1204. In high voltage applications, a singleESD protection circuit such as the ESD protection circuit 200 shown inFIG. 13 may not provide a reliable ESD protection. By contrast, aplurality of ESD protection circuits 200 connected in series may providean adjustable ESD protection breakdown voltage as well as an adjustableESD protection current. As shown in FIG. 13, the ESD protection circuits200 connected in series are substantially identical. It should be notedthat “substantially identical” means the same design but could bedifferent from each other due to fabrication process variations.

In FIG. 13, if an ESD event occurs, a voltage spike is applied betweenthe I/O pad 1206 and the VSS pad 1204. The series-connected ESDprotection circuits may turn on nearly simultaneously. Each ESDprotection circuit provides an ESD protection breakdown voltage. The sumof all series-connected ESD protection circuits' breakdown voltagesclamps the I/O pad's voltage 1206 to a level below the maximum ratingvoltage of the internal circuits 1202, so that the internal circuits1202 are protected.

As described above with respect to FIG. 12, placing an ESD device (e.g.,ESD protection device 200) between the I/O pad 1206 and the VSS pad 1204in FIG. 13 is merely an example. One skilled in the art will recognizemany variations, alternatives, and modifications, such as connecting theESD device between the VDD pad 1208 and the VSS pad 1204 as indicated bythe dashed line in FIG. 13.

Although embodiments of the present invention and its advantages havebeen described in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A semiconductor device comprising: a substrate; atransistor in the substrate, comprising: a collector comprising ann-type region; a base comprising a first p-type region; and an emittercomprising an N well; a first P well in the substrate and under thefirst p-type region; a second P well in the substrate, wherein the firstP well and the N well extend into the second P well; a first isolationregion in the substrate between the n-type region and the first p-typeregion; a second isolation region in the substrate between the n-typeregion and the N well; and a PN junction connected in series with thetransistor, wherein the PN junction comprises the N well and a secondp-type region over the N well.
 2. The semiconductor device of claim 1,wherein the second p-type region is a p-type metal contact.
 3. Thesemiconductor device of claim 2, wherein a lower surface of the p-typemetal contact facing the substrate contacts and extends along an uppersurface of the N well.
 4. The semiconductor device of claim 1, whereinthe n-type region, the first p-type region, the N well, the firstisolation region, and the second isolation region have a coplanar uppersurface.
 5. The semiconductor device of claim 4, wherein the firstisolation region extends continuously from the first p-type region tothe n-type region, and wherein the second isolation region extendscontinuously from the n-type region to the N well.
 6. The semiconductordevice of claim 5, wherein the first isolation region and the secondisolation region extend deeper into the substrate than the n-type regionand the first p-type region, wherein the N well extends deeper into thesubstrate than the first isolation region and the second isolationregion.
 7. The semiconductor device of claim 1, wherein the first P wellcontacts and extends along a lower surface of the first p-type region.8. The semiconductor device of claim 7, wherein the first P well furthercontacts and extends along a sidewall of the first isolation region anda first portion of a bottom surface of the first isolation region. 9.The semiconductor device of claim 8, wherein the second P well contactsand extends along a second portion of the bottom surface of the firstisolation region.
 10. The semiconductor device of claim 1, wherein the Nwell contacts and extends along a sidewall of the second isolationregion and a first portion of a bottom surface of the second isolationregion, wherein the second P well contacts and extends along a secondportion of the bottom surface of the second isolation region.
 11. Thesemiconductor device of claim 10, wherein the second P well contacts andextends along a lower surface of the n-type region, wherein there is adepletion region at the lower surface of the n-type region.
 12. Asemiconductor device comprising: a substrate; a diode having a PNjunction, the diode comprising a metal contact and an N well, whereinthe N well is in the substrate, and the metal contact is over the Nwell; a transistor in the substrate and connected in series with thediode, wherein the transistor comprises an emitter, a collector, and abase, wherein the collector comprises an n-type region, the basecomprises a p-type region, and the emitter comprises the N well; a firstP well in the substrate and under the p-type region; and a second P wellin the substrate, wherein the second P well extends along a lowersurface of the n-type region, and at least partially surrounds the firstP well and the N well.
 13. The semiconductor device of claim 12, whereinthe metal contact is a p-type metal contact.
 14. The semiconductordevice of claim 12, wherein the n-type region is in the substrate andlaterally between the N well and the p-type region.
 15. Thesemiconductor device of claim 14, further comprises: a first isolationregion in the substrate and extending continuously from the p-typeregion to the n-type region; and a second isolation region in thesubstrate and extending continuously from the n-type region to the Nwell.
 16. The semiconductor device of claim 15, wherein the first P wellcontacts and extends along the p-type region and a first portion of abottom surface of the first isolation region, wherein the N wellcontacts and extends along a first portion of a bottom surface of thesecond isolation region, wherein the second P well contacts and extendsalong a second portion of the bottom surface of the first isolationregion and a second portion of the bottom surface of the secondisolation region.
 17. A semiconductor device comprising: a substrate; atransistor in the substrate, the transistor comprising: a base; anemitter; and a collector, wherein the collector is disposed in thesubstrate laterally between the base and the emitter; a first isolationregion in the substrate between the base and the collector; a secondisolation region in the substrate between the emitter and the collector;a third isolation region in the substrate, wherein the emitter isbetween the second isolation region and the third isolation region; anda diode connected in series with the transistor, the diode comprising ametal contact forming a PN junction with the emitter of the transistor,wherein the metal contact overlies the emitter and extends continuouslyfrom the second isolation region to the third isolation region.
 18. Thesemiconductor device of claim 17, wherein the base is a first dopedsemiconductor region in the substrate, the collector is a second dopedsemiconductor region in the substrate, and the emitter is a first wellregion in the substrate.
 19. The semiconductor device of claim 18,further comprising: a second well region in the substrate under thefirst doped semiconductor region; and a third well region in thesubstrate, wherein the first well region and the second well regionextend into the third well region, wherein the first well region has afirst dopant of a first type, the first type being n-type or p-type,wherein the second well region and the third well region has a seconddopant of a second type different from the first type, the second typebeing p-type or n-type.
 20. The semiconductor device of claim 19,wherein the first well region covers a first portion of a lower surfaceof the second isolation region, and the second well region covers afirst portion of a lower surface of the first isolation region, whereinthe third well region covers a second portion of the lower surface ofthe first isolation region and a second portion of the lower surface ofthe second isolation region.